1. Technical Field
The present invention relates in general to a method and system for data processing and in particular to a method and system for interfacing an upgrade processor to a data processing system having a disparate data path width. Still more particularly, the present invention relates to a method and system for interfacing a upgrade processor which processes transactions in m-byte packets of data to a data processing system which performs transactions utilizing n-byte packets of data.
2. Description of the Related Art
Since the advent of personal computers, designers and manufacturers have sought to enhance the performance and prolong the useful life of their machines. One familiar technique which enhances both the performance and longevity of a personal computer is to upgrade the personal computer by installing an upgrade processor. Thus, if a user is satisfied with the performance of the other components within the personal computer system, the user may enjoy the enhanced performance of a new processor without the expense of replacing the remainder of the personal computer system. For example, as is well-known in the art, a user may upgrade a 486 personal computer operating at 33 MHz to a 66 MHz machine by replacing the standard 486 processor with a 486 DX2 processor.
Although it is advantageous for a user to be able to upgrade a personal computer in the above described manner, the requirement that the upgrade processor be compatible with the personal computer system can stifle innovation in processor architectures. In order to remain compatible with existing hardware and software, manufacturers often retain instruction sets and signaling protocols which may not provide optimal performance. For example, recent technological advances have made reduced instruction set (RISC) processors more advantageous than traditional complex instruction set (CISC) processors in many applications. When CPUs were much faster than memory, it was advantageous for processors to perform multiple operations per instruction since processors would otherwise waste cycle time waiting for the memory to deliver instructions. Now that CPU speed and memory access time have become more balanced, RISC architecture has become more feasible, assuming that the memory hierarchy is able to deliver one instruction plus data each cycle. Other recent advances in state-of-the-art processor architecture include the incorporation of on-chip interconnection and memory utilizing VLSI fabrication techniques and the increase of the data path width of processors from 32 to 64 bits. Although processors incorporating these advances in CPU technology provide greatly enhanced performance, they are not readily available for use as upgrade processors since they are often incompatible with existing computer systems.
It is known in the art to upgrade a personal computer system having a 32-bit processor and a 32-bit data bus with an 64-bit processor or a 32-bit processor with a 64-bit data path. In one technique, the 64-bit processor is directly connected to the 32-bit data bus and reads data in serial 32-bit packets. In a second upgrade system, the 64-bit processor is interfaced to two parallel 32-bit buses. As with the first technique, in the second, data is still input to the 64-bit processor in two 4-byte packets, rather than a true 8-byte format. With either interface technique, the computer system does not receive the full benefit of the enhanced performance of the 64-bit upgrade processor bus since processor cycle time is consumed by either additional bus cycles or internal data formatting. Consequently, it would be desirable to provide a method and system for efficiently interfacing a processor which performs transactions utilizing m-byte packets of data with a personal computer system which performs transactions utilizing n-byte packets of data where n&lt;m.
A second issue that must be addressed when interfacing a upgrade processor to a personal computer system is the scheme employed to arbitrate between the upgrade processor and bus master devices within the personal computer system for ownership of the system bus. Determining an efficient arbitration scheme is complicated by the fact that the upgrade processor may have a different arbitration protocol from that of the personal computer system if their architectures are dissimilar. For example, some processor architectures, such as the x86 architecture, can utilize a uni-directional (asynchronous) bus acquisition protocol, in which the requesting bus master expects to receive control of the system bus after asserting a request signal. In other architectures, bus masters utilize a bi-directional handshake bus acquisition protocol in which both a request signal by a second bus master and an acknowledge signal from the arbiter are required before the second bus master assumes control of the bus from the first bus master. Prior art systems do not support interfacing upgrade processors in personal computer systems which have incompatible arbitration protocols. Consequently, it would be desirable to provide a method and system for interfacing an upgrade processor to a personal computer system which utilizes a dissimilar arbitration protocol.